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Clock Sync Generator
SDA 9257
Preliminary Data Features
q q q q
MOS IC
q q q q q q
All settings made by I2C Bus PLL lock-in behavior can be set to TV- or VCR mode Automatic clamping of CVBS input Provides all horizontal and vertical sync signals and clocks for operating PAMUX, analog color decoders, the A/D converters, PSND and Featurebox Free-running capability Frequency generator function possible with digitally P-DIP-28-1 adjustable frequency Lock-in function of the PLL on CVBS also possible with externally supplied 24-MHz or 27-MHz clock Multi-standard operation (50 Hz, 60 Hz; PAL, NTSC, SECAM) Vertical noise suppression and 50/60-Hz detection Serial digital output for actual frequency value and CVBS-black level
Applications
q q q q
Memory based image improvement with analog color decoder Memory based image improvement with digital multi-standard decoder Free-running sync generator Digital frequency synthesizer
Type SDA 9257 Functional Description
Ordering Code Q67100-H5038
Package P-DIP-28-1
The clock sync generator consists essentially of the following function blocks (refer to block diagram): Analog clamping 7-bit, 27-MHz A/D converter Sync processor with digital horizontal PLL, vertical sync processor and pulse generator Clock generator with discrete timing oscillator, D/A converter, analog PLL and divider, as well as a crystal oscillator q I2C Bus interface q Button flutter elimination
q q q q
Semiconductor Group
182
01.94
SDA 9257
Circuit Description 1 Horizontal PLL (HPLL)
The CVBS is clamped before A/D conversion such that the H-sync pulse level is applied to the analog ground. Conversion takes place with 7 bits and a nominal frequency of 27 MHz. The digital HPLL filters the signal with a cutoff frequency of 1 MHz for a decimated clock frequency of 13.5 MHz, then measures the black level, calculates the sync threshold and determines the phase difference between the horizontal pulse and its own phase position. By means of digital PI filtering an increment is gained from this for the Discrete Timing Oscillator (DTO). The PI filter can be set by the bus so that the lock-in behavior of the PLL is optimal in relation to either the TV or VCR mode. The DTO generates a saw-tooth with a frequency that is proportional to the increment, i.e. one quarter of the clock frequency on pin CLK1 (nominally 27 MHz). The saw-tooth is converted into a sinusoidal clock signal by means of sin ROMs and D/A converters and applied to an analog PLL which quadruples the frequency and minimizes residual jitter. In this manner a clock is provided that is line-locked with the CVBS-input signal. The ratio of this clock frequency to the horizontal frequency of CVBS can be set to the values 1728, 1716 or 1536 by the I2C Bus. The digital horizontal PLL supplies a further composite sync signal derived directly from the CVBS, a noise-suppressed horizontal pulse and a non-suppressed vertical pulse obtained by digital integration of the main equalizing pulses. An integration time of 26.6 s or 11.3 s can be set by the I2C Bus. The HPLL is driven in the "external clock mode" by the 24-MHz clock supplied by pin CKE and locks onto CVBS by continually locking the relationship between the input clock and the horizontal frequency of CVBS (768 32). The HPLL can lock onto a composite sync signal using application circuit 5. The edges on pin CVBS should not be steeper than 100 ns.
2
Vertical Sync Processing
Vertical sync processing consists of:
q 625/525 line detection q Vertical noise suppression
The 625/525 line detector measures the range of lines within a field into which the vertical pulses will fall that were obtained from the CVBS signal by integration. By taking the average of the individual measurements with two up/down counters, the status bits "FF" and "FFGF" (refer to timing diagram 8 and I2C Bus) are obtained. When vertical noise suppression is switched on (VOFF = 0), the vertical pulse obtained from the CVBS signal by integration is admitted only within a preset window (refer to timing diagram 8) and appears as a VS pulse. The width of the window can be set with the I2C Bus bit VWW. In the temporary absence of vertical pulses in CVBS, a continuous VS can be generated by switching on a "flywheel mode" (SCHW = 1) provided that the number of lines per field in CVBS is 312.5 or 262.5 respectively.
Semiconductor Group
183
SDA 9257
When interference to CVBS is heavy, missing vertical pulses can be supplemented by switching on the flywheel mode and vertical interference pulses can be eliminated by switching on the noise suppression circuitry. Noise suppression and the flywheel mode can be enabled independently of each other. There is also the possibility of generating VS in the free-running mode. The VS pulses are then completely independent of the vertical sync pulse in CVBS. When FREE = 1, a VS pulse is generated every 262.5 or 312.5 lines (VF = 1 or 0 respectively). Free-running generation of VS occurs every 262 or 312 lines in the terminal mode (TERM = 1). The two fields can be identified by means of status bit HB. It toggles for every field but is set to 0 whenever the vertical pulse occurs within the first half of a line and within the noise-reduction window (start of the first field).
3
Pulse Generation
The clock sync generator supplies the following pulses:
q q q q q q q q
q q
q
HS VS BLN Two clamping pulses (H1 and H2) Either a sandcastle (SC) or a super sandcastle (SSC) pulse or a composite sync (CS) The HS pulse is 32 CLK1 clock periods long and can be shifted by the I2C Bus in increments of 8 CLK1 clock periods each (see timing diagram 1). For the VS pulse refer to vertical noise suppression With the BLN pulse the start time (high-to-low edge) and the stop time (low-to-high edge) can be set within a certain range of lines in increments of two CLK1 clock periods by the I2C Bus. The timing of BLN does not change during the field blanking interval. The start time (low-to-high edge) and stop time can similarly be set in increments of two CLK1 clock periods for pulses H1 and H2. The composite sync signal is derived from the CVBS, after it has passed through a low-pass filter, by means of the sync threshold in the HPLL and is also provided with circuitry to suppress noise which might occur due to very noisy CVBS (refer to timing diagrams 4 and 5, and diagram 1). An external transistor stage is required to generate sandcastle or super sandcastle pulses and inserts the missing burst key in the pulse on the SC pin, which has only a zero, vertical- and horizontal-blanking level. For this purpose the inverse burst-key signal is available at pin SINC for triggering the transistor base (refer to application circuit 6). The start time of the horizontal blanking level may be defined in increments of two CLK1 clock periods over a wide range of lines by the I2C Bus.
Semiconductor Group
184
SDA 9257
4
Miscellaneous Circuit Sections
q To suppress bottom flutter in VCR mode, the frequency of the clock can be "hold" by "freezing"
the increment of the HPLL. The vertical-frequency "freezing-time" starts a number of lines (programmable by the I2C Bus) before the vertical pulse and then lasts for a number (programmable) of lines (refer to timing diagram 2). The settings do not depend on I2C-bit VCRTV. q The increment of the HPLL, the black level and the status bits are output serially on the SINC pin (optionally to the sandcastle pulse) and are therefore available for a digital color decoder, for instance. Because the frame of these line-frequency output begins with a start bit (low) it can be detected independently of the phase of HPLL (refer also to timing diagram 3). q An active low reset is available for other chips at pin RES. It is reset when the chip supply VDD is switched on or when voltage glitches occur in it. It is not cancelled until the crystal oscillator resonates and the two device supplies VDD and VDDA are applied. The minimum length of time is 1 ms.
5
External Clock Mode of the HPPL
The HPPL locks onto the CVBS signal for the following operating ranges when the chip is operated with a clock frequency supplied on pin CKE (SCLE bit at 1):
Control Bit HPPL 1 0 1 1 HPPL 0 X 0 1
Clock Frequency Range on CKE 26.1 ... 27.9 MHz 26.1 ... 27.9 MHz 23.1 ... 24.9 MHz
The jitter on output pulses HS, VS, BLN, H1 and H2 and output clocks CLK1 and CLK2 is several CLK1-clock periods long.
Semiconductor Group
185
SDA 9257
Detailed Circuit Description Description of I2C Interface Slave Address: 1 0 1 1 0 B C B: Equal to the value set on pin ADR1 C: Equal to the value set on pin ADR0
Receiver Format: S Slave Address 0A Sub Address A Data Byte AP
S: Start condition A: Acknowledge P: Stop condition
Semiconductor Group
186
SDA 9257
Synoptical Table of Data Byte Formats Receiver Register
Pin Control HPLL Control V Process. - and VCO Control
SUBADDR. (MSB)
00 01 02 03 OEFB HPLL1 FREE INC07 INC15 BON8 BOF8 H10N8 H10F8 H20N8 H20F8 HS0N8 SC0N8 FI0N4 SCL2 HPLL0 VOFF INC06 INC14 BON7 BOF7 H10N7 H10F7 H20N7 H20F7 HS0N7 SC0N7 FI0N3 SCLE RSTH VF INC05 INC13 BON6 BOF6 H10N6 H10F6 H20N6 H20F6 HS0N6 SC0N6 FI0N2
Data Bits (LSB)
CLKDI SSC1 SSC0 VCRT VCO2 INC02 INC10 BON3 BOF3 H10N3 H10F3 H20N3 H20F3 HS0N3 SC0N3 FILE3 I1 FRZIN VCO1 INC01 INC09 BON2 BOF2 H10N2 H10F2 H20N2 H20F2 HS0N2 SC0N2 FILE2 SCHW EXINC VCO0 INC00 INC08 BON1 BOF1 H10N1 H10F1 H20N1 H20F1 HS0N1 SC0N1 FILE1 VTHRE CLOF VWW INC04 INC12 BON5 BOF5 H10N5 H10F5 H20N5 H20F5 HS0N5 SC0N5 FI0N1 TERM INC03 INC11 BON4 BOF4 H10N4 H10F4 H20N4 H20F4 HS0N4 SC0N4 FILE4
External Clock04 Frequency Control BLN Start Time BLN Stop Time H1 Start Time H1 Stop Time H2 Start Time H2 Stop Time HS Start Time SC Start Time FRZINC TIME 05 06 07 08 09 10 11 12 13
(Automatic incrementing of the subaddress) When operating voltage is applied (POR), all registers are set to 0.
Pin Control (subaddress 00) Output Enable by Featurebox Signals BLN, HS, VS outputs tristate BLN, HS, VS outputs enabled Selection of Clock Frequency on CLK2 13.5 MHz (nominal) 27 MHz (nominal) Control Bit OEFB 0 1 Control Bit SCL2 0 1
Semiconductor Group
187
SDA 9257
Selection of Clock for Chip Operation A line locked clock is generated by the internal PLL Clock source is CLE. The radio between the horizontal frequency in CVBS and CLK1 depends on control bits HPLL0 and HPLL1* Clock Out Disable CKL1 and CKL2 tristate CKL1 and CKL2 enabled Selection of Function on SC and SINC SC-Pin Function Tristate Super sandcastle Sandcastle Composite sync without burst key SINC-Pin Function Tristate Burst key inverted Serial increment and status bits
Control Bit SCLE 0
Control Bit CLKDI 1 0 Control Bits SSC1 0 0 1 1 SSC0 0 1 1 0
Level on I1 Low High Mode of Vertical Pulse Generation No flywheel mode Flywheel mode
*
Control Bit I1 0 1 Control Bit SCHW 0 1
Pin CLE should most definitely be connected to ground in this instance in order to minimize output signal jitter
Semiconductor Group
188
SDA 9257
HPLL Control (subaddress 01) Relationship between Horizontal Frequency in CVBS and Frequency on CKL1 1728 1716 1536 Initiation of a Reset for HPLL No function HPLL is reset once, new lock-in process starts Minimum Sync Pulse Length from which a Vertical Pulse is Detected 26.6 s 11.3 s CVBS Clamping ON/OFF Clamping ON Clamping OFF Selection of HPLL Lock-In Behavior Optimum for VCR Optimum for CVBS from network Freezing of the Actual Value of Clock Frequency No function Instantaneous increment is freezing so that the instantaneous frequency value is frozen and there is no lock-in function of HPLL Selection of Increment for Determining Clock Frequency Increment from HPLL Increment corresponding to I2C Bus bits INC00 ... INC15 (frequency generator mode)
*)
Control Bits HPLL1 0 1 1 HPLL0 *) 0 1
Control Bit RSTH 0 1 Control Bit VTHRE 0 1 Control Bit CLOF 0 1 Control Bit VCRTV 0 1 Control Bit FRZINC 0 1
Control Bit EXINC 0 1
don't care
Semiconductor Group
189
SDA 9257
Vertical Processor and VCO Control (subaddress 02) Generation of V Pulse V derived from CVBS Free-running generation; vertical frequency is determined by VF bit, VOFF bit is enabled, SCHW bit should be set to 1 Vertical Noise Suppression Noise suppression enabled No noise suppression Number of Lines per Field 312.5 or 312 262.5 or 262 Control Bit FREE 0 1
Control Bit VOFF 0 1 Control Bit VF 0 1
Note: VF must be set to the number of lines present in CVBS for flywheel and noise suppression modes. VF is determined by the number of lines per field for the free-running or terminal mode. Width of Window in Vertical Processing Wide window in vertical noise suppression mode and for detection of status bits FF and FFGF Narrow window (refer also to timing diagrams 8 and 9) Number of Lines per Field Generated in Free-Running Mode 312 262 312.5 262.5 344 288
x: don't care
Control Bit VWW 0 1 Control Bits
FREE x x 1 1 1 1
TERM 1 1 0 0 0 0
SCHW x x 1 1 0 0
VF 0 1 0 1 0 1
VOFF x x x x x x
Semiconductor Group
190
SDA 9257
Center Frequency (of VCO) Approx. 22.4 MHz Approx. 24.0 MHz Approx. 25.6 MHz Approx. 27.0 MHz Approx. 29.0 MHz Approx. 31.0 MHz Approx. 33.0 MHz Approx. 35.0 MHz
Control Bits VCO2 0 0 0 0 1 1 1 1 VCO1 1 1 0 0 1 1 0 0 VCO0 1 0 1 0 1 0 1 0
Note: The pull-in range of the VCO is 8 %, irrespective of the center frequency External Clock Frequency Setting (subaddresses 03 and 04) Clock Frequency on CLK1 (FQ = XTAL Frequency, [INC] = Digital Value of INC15 ... INC00) EXINC bit must be set) F = FQ x 4 * 65536/262144 = FQ F = FQ x 4 * (65536 + [INC])/262144 F = FQ x 4 * (65536 + 65535)/262144 = 2 x FQ Control Bits (MSB) INC15 0 1 0 1 (binary offset) INC14 . . . ... ... ... (LSB) INC00 0 1
Note: When clock frequencies below 24 MHz or above 29 MHz are selected, the VCO should be set with control bits VCO2 ... VCO0 as well. Clock jitter may rise when crystal clock FQ is changed.
Semiconductor Group
191
SDA 9257
All times quoted below refer to a nominal frequency of 27 MHz on CLK1 BLN Start Time (subaddress 05) BLN Start Time in Relation to Reference Time (refer also to timing diagram 1) Time 9.62 s . . . 0.22 s 0.15 s . . . - 9.25 s - 125 +3 +2 Number in 13.5-MHz Clock Periods + 130 - (- 128) + 2* . . . - (- 1) + 2* - ( 0) + 2* . . . - (+ 127) + 2* 0 1 1 1 0 1 0 1 0 BON8 1 Control Bits (Two's Complement) (LSB)
BON7 0
BON6 0
... ... . . . ... ... . . . ...
BON2 0
BON1 0
1 0
1 0
1
1
BLN Stop Time (subaddress 06) BLN Stop Time in Relation to Reference Time Time + 0.22 s . . . + 9.63 s + 9.0 s Number in 13.5-MHz Clock Periods +3 . . . + 130 + 131 . . . + 19.11 s
*
Control Bits (One's Complement) BOF8 0 BOF7 0 BOF6 0 ... ... . . . BOF2 0 BOF1 0
0 + 3*
127 + 3* 128 + 3*
0 1
1 0
1 0
... ... . . .
1 0
1 0
+ 258
255 + 3*
1
1
1
...
1
1
Due to internal delays
Semiconductor Group
192
SDA 9257
H1 Start Time (subaddress 07) and H1 Stop Time (subaddress 08) (identical coding) H1 Start and Stop Times in Relation to Reference Time Time + 4.88 s . . . + 0.222 s + 0.148 s . . . - 4.51 s - 4.58 s . . . - 9.26 s - 9.33 s - 125 - 126 . . . - 13.95 s
*
Number in 13.5-MHz Clock Periods + 66 . . . +3 +2 . . . - 61 - 62 . . . - (+ 127) + 2* - (+ 128) + 2* - (+ 63) + 2 - (+ 64) + 2* - (- 1) + 2* - (+ 0) + 2* - (- 64) + 2*
Control Bits . . . H10N8 H10N7 H10N6 ... H10F8 H10F7 H10F6 ... 1 1 0 . . . 1 0 1 0 1 0 . . . 0 0 0 1 1 0 . . . 0 1 1 0 1 0 . . . ... ... ... ... ... ... ...
H10N2 H10N1 H10F2 H10F1 0 0
1 0
1 0
1 0
1 0
1 0
1 0
- 189
- (+ 191) + 2*
1
0
1
...
1
1
Due to internal delays
Semiconductor Group
193
SDA 9257
H2 Start Time (subaddress 09) and H2 Stop Time (subaddress 10) (identical coding) H2 Start and Stop Times in Relation to Reference Time Time + 14.32 s . . . + 9.70 s + 9.63 s + 9.56 s . . . + 0.222 s + 0.148 s + 0.074 s . . . - 4.51 s - 61 +3 +2 +1 . . . - (+ 63) + 2* 0 0 Number in 13.5-MHz Clock Periods + 194 . . . + 131 + 130 + 129 . . . - (- 1) + 2* - ( 0) + 2* - (+ 1) + 2* 1 0 0 1 0 0 - (- 129) + 2* - (- 128) + 2* - (- 127) + 2* 0 1 1 1 0 0 - (- 192) + 2* Control Bits H20N8 H20N7 H20N6 H20F8 H20F7 H20F6 0 1 0 . . . 1 0 0 . . . 1 0 0 . . . 1 ... 1 1 ... ... ... 1 0 0 1 0 1 ... ... ... 1 0 0 1 0 1 ... ... ... H20N2 H20N1 H20F2 H20F1 0 0
HS Start Time (subaddress 11) HS Start Time in Relation to Reference Time Time Number in 13.5-MHz Clock Periods - (- 96) + 2* . . . +5 +1 - . . . - (118) * 4 + 1* - (119) * 4 + 1* 0 0 - (- 1) * 4 + 1* - ( 0) * 4 + 1* - (+ 1) * 4 + 1* 1 0 0 Control Bits
HS0N8 HS0N7 HS0N6 1 0 . . . 1 0 0 . . . 0 0 1 1 1 0 0 1
.... 0000
HS0N1 0
- 28.52 s + . . . + 0.37 s + 74 ns - 222 ns . . .
1111 0000 0000
1 0 1
- 34.89 s - 471 - 35.18 s - 475
* Due to internal delays
1011 1011
0 1
Semiconductor Group
194
SDA 9257
SC Start Time (subaddress 12) Start Time of H Insertion in the SC or SSC Pulse Time + 9.55 s Number in 13.5-MHz Clock Periods + 129 . . . 74 ns +1 . . . - 9.33 s - 126 - (0) + 1* 0 0 (+ 128) + 1* Control Bits (+) (Two's Complement) (LSB) SC0N8 SC0N7 SC0N6 1 0 0 . . . 0 . . . 0 1 1 ... 1 1 ... 0 0 ... ... SC0N2 SC0N1 0 0
- (+ 127) + 1*
Freezing of Actual Clock Frequency in Number of Lines Near the Vertical Pulse (subaddress 13) Start of Clock Frequency in Number of Lines before the Vertical Pulse 0 (no freezing) 1 . . . 15 Duration of Clock Frequency Freezing in Number of Lines 0 (no freezing) . . . 15
* Due to the internal delays
Control Bits FION4 0 0 FION3 0 0 . . . 1 1 1 1 FION2 0 0 FION1 0 1
Control Bits FILE4 0 FILE3 0 . . . 1 1 1 1 FILE2 0 FILE1 0
Semiconductor Group
195
SDA 9257
Transmitter Format: S Slave Address 1A Status Byte Status Bits
KOI THREUM FFGF FF HB POR POR POR
AP
N: no acknowledge
Status Byte
Absolute Difference in Time between the Horizontal Sync Pulse in CVBS and the HPLL Greater than or equal to 2.4 s Less than 2.4 s Absolute Difference in Time between the Horizontal Sync Pulse in CVBS and the HPLL Greater than 0.6 s Less than 0.6 s for 8 or more successive lines (i.e. HPLL well locked in) Identified Number of Lines per Field (refer also to timing diagram 9) Less than 287 Greater than or equal 287 Between 262 and 264 Between 312 and 314 Between 250 and 275 Between 300 and 325 Field Detection (Applicable to Interlace Only) First field Second field
Status Bit KOI 0 1 Status Bit THRELIM 0 1
Status Bits FFGF 0 0 1 1 1 1 FF 1 0 1 0 1 0 Status Bit HB 0 1
Control Bit VWW x x 1 1 0 0
Status bit POR: POR is set by power on reset or by setting the bit RSTH. POR is reset after reading the status byte.
Semiconductor Group
196
SDA 9257
Block Diagram
Semiconductor Group
197
SDA 9257
Pin Configuration (top view)
Semiconductor Group
198
SDA 9257
Pin Definitions and Functions Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I1 T1 T2 RES VS Function I C Bus bit I1 Test pin Reset Vertical sync pulse
2
Description Pin (e. g. for source selection) set by I2C Bus Test pin, connect to VSS Reset output, active low Tristate vertical pulse output Substrate bias Analog supply Analog ground High reference voltage CVBS input, 2 VSS nom. I2C-chip select Output for serial increment or inverse burst-key output SC, SSC or CS output Tristate clock output, 24-32 MHz Tristate clock output, 12-16 MHz or 24-32 MHz External clock input, 24-32 MHz Clamping pulse input Crystal connection Crystal connection (clock input) Digital supply Digital ground Clamping pulse output Crystal clock output Clock input, I2C Bus Bi-directional data, I2C Bus Tristate output for Featurebox Tristate H-pulse output
Smoothing and test pin Internal smoothing, test pin
VBB VDDA VSSA
HREF CVBS ADR0 ADR1 SINC SC CLK1 CLK2 CLKE H2 X2 X1
VBB
+5V Ground +3V CVBS Address 0 Address 1 Serial increment Sandcastle Clock 1 Clock 2 External clock Clamping pulse Xtal 2 Xtal 1 +5V Ground Clamping pulse Xtal clock Clock I2C Bus Serial data I2C Bus Blanking out Horizontal sync pulse
VDD VSS
HI XQL SCL SDA BLN HS
Semiconductor Group
199
SDA 9257
Absolute Maximum Ratings (all voltages are referred to VSS) Parameter Supply voltage Voltages on SCL, SDA, ADR1, ADR0, TEST, XQL, CKE and HREF CVBS for AC coupling for DC coupling Ambient temperature Storage temperature Total power dissipation Thermal resistance Supply voltage difference Operating Range Supply voltage Ambient temperature Symbol Limit Values min. max. 6 6 V V V V V 70 125 1 39 0.25 C C W K/W V - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 20 - 20 Unit Remarks
VDD VDDA VI VI VI TA Tstg Ptot Rth VDD -VDDA
VDD VDDA TA
4.5 4.5 - 10
5.5 5.5 70
V V C
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200
SDA 9257
Characteristics TA = 25 C (all voltages are referred to VSS) Parameter Supply current Symbol min.
IDD
Limit Values typ. max. 100 50
Unit mA mA
Test Condition No load
IDDA
CVBS Input Input signal H-sync pulse level of CVBS Input capacitance Input frequency Internal resistance of CVBS source Input HREF Input voltage Input current Inputs ADR1, ADR0 L-input voltage H-input voltage Input capacitance
VIPP VSY
0.25 0
2
4 1 10 12
V V A pF MHz to avoid aliasing With clamping and 10 nF clamping capacitor When internal clamping is not used
Input leakage current II
VI = 0 V
CI f RI
0
12 100
VI II
2.7
3 15
V A
VI = 3 V
VIL VIH CI
0 2
0.8
V V A pF
VDD
10 7
Input leakage current II
VI = 5.5 V
SCL Input - SDA Input/Output L-input voltage H-input voltage Input capacitance Input frequency Max. capacitance on bus
VIL VIH CI fSCL Cmax
0 3
1.5
V V pF A kHz pF
VDD
10 7 100 400
Input leakage current II
VI = 5.5 V
Semiconductor Group
201
SDA 9257
Characteristics (cont'd) TA = 25 C (all voltages are referred to VSS) Parameter Fall time (acknowledge) SDA upon acknowledge CKE Input L-input voltage H-input voltage Input capacitance Symbol min. Limit Values typ. max. 0.3 0 0.4 s V from 3 to 1 V Unit Test Condition
tF VAL
IAL = 3 mA
VIL VIH CI fCKE tR, tF
0 2
0.8
V V pF A MHZ ns
VDD
10 7 35 5
Input leakage current II Input frequency Transition times
VI = 5.5 V
Crystal Connections X1, X2 Crystal frequency Crystal type Equivalent parallel C Crystal resonant impedance Pin capacitance External capacitance
fc
20.44
20.50
20.56
MHZ
Overall tolerance incl. temperature drift
Fundamental crystal
CO ZR CI Cext
7 25 7 30
pF pF pF
VS, HS, H1, H2, BLN, I1 and RES Outputs L-output voltage H-output voltage Load capacitance Transition times Output delay time Output hold time
VQL VQH CL tR, tF tQD tQH
0 2.4
0.4
V V pF ns ns ns
I = 1.6 mA I = - 0.5 mA CL = 30 pF
VDD
50 5 25
6
Semiconductor Group
202
SDA 9257
Characteristics (cont'd) TA = 25 C (all voltages are referred to VSS) Parameter Symbol min. CLK1, CLK2 Outputs L-output voltage H-output voltage Load capacitance Transition times Low time High time Low time High time Skew Jitter (rms) Limit Values typ. max. Unit Test Condition
VQL VQH CL tR, tF tWL13 tWH13 tWL27 tWH27 tSK tj
0 2.4
0.4
V V pF ns ns ns ns ns
I = 1.6 mA I = - 0.5 mA CL = 30 pF
13.5 MHz 8 % 13.5 MHz 8 % 27 MHz 8 % 27 MHz 8 % TV-time constant, 0.6 V nominal sync amplitude
VDD
50 5
26 26 10 10 0 4 3 25.72 27.00 28.26
ns ns MHz
Frequency range f when PLL is locked at CVBS SINC Output L-output voltage H-output voltage Load capacitance Transition times SC Output H-output voltage Vertical level output voltage L-output voltage Load capacitance Transition times Transition times Output delay time Output hold time
VQL VQH CL tR, tF
0 2.4
0.4
V V pF ns
I = 1.6 mA I = - 0.5 mA CL = 30 pF
VDD
50 5
VQH VQV VQL CL tR, tF tR, tF tQD tQH
4.4 2.1 2.5 0.4
4.9 2.6 0.8 30 5 100 25
V V V pF ns ns ns ns
I = - 0.5 mA
for SSC I = - 0.3 mA
I = 1.6 mA
for composite sync for SC or SSC for composite sync for composite sync
6
Semiconductor Group
203
SDA 9257
Timing Diagram 1 I2C Bus Programming Areas of Horizontal-Frequency Pulses Semiconductor Group 204
SDA 9257
(In this example the frequency value was frozen 13 lines before the VS pulse and for a duration of 11 lines). Timing Diagram 2 I2C Bus Programming Area in which Clock Frequency Value Generated by HPLL can be Frozen
Semiconductor Group
205
SDA 9257
Timing Diagram 3 Serial Transfer of Increment, Black Level and Status Bits on Pin SINC (once for each TV line)
Semiconductor Group
206
SDA 9257
Timing Diagram 4 Sandcastle, Super Sandcastle, VS and Composite Sync CS at 50 Hz Semiconductor Group 207
SDA 9257
Timing Diagram 5 Sandcastle, Super Sandcastle, VS and Composite Sync CS at 60 Hz Semiconductor Group 208
SDA 9257
Timing Diagram 6 Sandcastle and Super Sandcastle Pulse
Semiconductor Group
209
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Timing Diagram 7 Output Clocks and Data
Semiconductor Group
210
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Timing Diagram 8 Window for Vertical Pulse Noise Suppression
Semiconductor Group
211
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Timing Diagram 9 Window for Detection of Number of Lines per Field Semiconductor Group 212
SDA 9257
Application Circuit 1 Featurebox Environment with Analog Color Decoder
Semiconductor Group
213
SDA 9257
Application Circuit 2 Featurebox Environment with Analog Color Decoder Semiconductor Group 214
SDA 9257
Application Circuit 3 CSG and PAMUX TDA 9045 Semiconductor Group 215
SDA 9257
Application Circuit 4 Input Circuit with Composite Sync as Source
Application Circuit 5 Possible Output Circuit for Generating Super Sandcastle
Semiconductor Group
216
SDA 9257
Frequency Response of Noise Suppression S of the Composite Sync Output Signal in Relation to CVBS Input
Semiconductor Group
217

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